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8520 used in Commodore and Amiga equipment

IC number

8520

IC function

CIA (Complex Interface Adapter)

Related components

6526 (predecessor)

Component documentation

IC number	Manufacturer	Documentation
8520	MOS Technology / CSG	Not available

Component versions

IC number	Package	Speed	CBM part number	CBM part description
8520	40-Pin DIP	1 MHz	318029-01 / 318029-02	MOS 8520 R4 Amiga CIA
8520A-1, 8520A-1PD, 8520PD	40-Pin DIP	2 MHz	318029-03	8520A-1 2MHz CIA
8520PL	44-Pin PLCC	1 MHz	391078-01	IC, CSG, 8520R4, CIA, 1MHz, 44-Pin PLCC
8520A-1PL	44-Pin PLCC	2 MHz	391078-02	IC, SM, LSI, Complex Int Adapt 8520A-1 PLCC 44

Positions

Device	Positions	Package	Speed
A1000	U6P (CIA-A), U6N (CIA-B)	DIP	1 MHz or 2 MHz
A2000	U10 (CIA-A), U11 (CIA-B)	DIP	1 MHz or 2 MHz
A2000CR	U300 (CIA-A), U301 (CIA-B)	DIP	1 MHz or 2 MHz
A500	U7 (CIA-A), U8 (CIA-B)	DIP	1 MHz or 2 MHz
A500 Plus	U7 (CIA-A), U8 (CIA-B)	DIP	1 MHz or 2 MHz
CDTV	U9 (CIA-A), U10 (CIA-B)	DIP	1 MHz or 2 MHz
A3000	U350 (CIA-A), U300 (CIA-B)	DIP	1 MHz or 2 MHz
A3000T	U350 (CIA-A), U300 (CIA-B)	DIP	1 MHz or 2 MHz
A600	U7 (CIA-A), U8 (CIA-B)	PLCC	1 MHz or 2 MHz
A4000	U350 (CIA-A), U300 (CIA-B)	PLCC	1 MHz or 2 MHz
A4000T	U550, U560	PLCC	1 MHz or 2 MHz
A1200	U7 (CIA-A), U8 (CIA-B)	PLCC	1 MHz or 2 MHz
A2232	U85	DIP	2 MHz
CD³² debug board	U6, U7	PLCC	1 MHz or 2 MHz
1571	U20	DIP	2 MHz
1581	U5	DIP	2 MHz

• CIA-A is sometimes called the odd CIA, CIA-B the even CIA.
• The 1571 diskdrive can use either the 6526A or 8520 CIA.
• The CIA is also used in the Draco and in several CD³² expansion units.

DIP package pinout for Amiga CIA-A use

Pin	Type	Name	Signal name
			A1000	A2000	A2000CR	A500 Rev. 5	A500 Rev. 6A/7	A500 Plus	CDTV	A3000, A3000T
1	Power	VSS	DGND	GND
2	I/O	PA0	OVL
3	I/O	PA1	_LED
4	I/O	PA2	_CHNG
5	I/O	PA3	_WPRO		_WPROT
6	I/O	PA4	_TK0		_TRK0
7	I/O	PA5	_RDY
8	I/O	PA6	_FIR0			_FIRE0				_FIR0
9	I/O	PA7	_FIR1			_FIRE1				_FIR1
10..17	I/O	PB0..PB7	P0..P7		PPD0..PPD7
18	Output	PC	_DRDY		PSTROBE	_STROBE via EMI511			_STROBE via RP29, EMI9	PSTROBE
19	Input	TOD	TICK	Connected to pin 2 of J34	TBASE	_VSYNC	Connected to pin 2 of JP7B		_VSYNC	TBASE
20	Power	VCC	+5V			VCC				+5V
21	Output	IRQ	_INT2
22	Input	R/W	_PRWD	_PRW via U15	R_W					CIARW
23	Input	CS	_VMA and A12 via a 74LS32					_ODD_CIA	_VMA and A12 via a 74LS32	_CIA0
24	Input	FLAG	_ACK		_PACK	_ACK via EMI521			_ACK via RP31, EMI18	_PACK
25	Input	O2	E					E via R109	E	ECLK
26..33	I/O	D7..D0	PD7..PD0		D7..D0					D23..D16
34	Input	RES	_RES		_BRST	_RESET				_IORST
35..38	Input	RS3..RS0	A11..A8							CIADR11..CIADR8
39	I/O	SP	KDAT	Connected to pin 2 of J3	_KBDATA via FB303	_KBDATA				_KBDAT
40	I/O	CNT	KCLK		_KBCLK	_KBCLOCK				_KBCLK

DIP package pinout for Amiga CIA-B use

Pin	Type	Name	Signal name
			A1000	A2000	A2000CR	A500	A500 Plus	CDTV	A3000, A3000T
1	Power	VSS	DGND	GND
2	I/O	PA0	BUSY		PBUSY	BUSY via EMI522		BUSY via RP30, EMI19	PBUSY
3	I/O	PA1	POUT		PPOUT	POUT via EMI523		POUT via RP30, EMI20	PPOUT
4	I/O	PA2	SEL		PSEL	SEL via EMI524		SEL via RP30, EMI21	PSEL
5	I/O	PA3	_DSR			DSR via U39, EMI536		DSR via U11, EMI30	_DSR
6	I/O	PA4	_CTS			CTS via U39, EMI535		CTS via U11, EMI29	_CTS
7	I/O	PA5	_CD			CD via U39, EMI537		CD via U11, EMI31	_CD
8	I/O	PA6	_RTS			RTS via U38, EMI553		RTS via U3, EMI27	_RTS
9	I/O	PA7	_DTR			DTR via U38, EMI531		DTR via U3, EMI26	_DTR
10	I/O	PB0	_STEP
11	I/O	PB1	DIR
12	I/O	PB2	_SIDE
13	I/O	PB3	_SEL0
14	I/O	PB4	_SEL1
15	I/O	PB5	_SEL2
16	I/O	PB6	_SEL3					unused	_SEL3
17	I/O	PB7	_MTR
18	Output	PC	unused
19	Input	TOD	_BHS			_HSYNC			_BHS
20	Power	VCC	+5V			VCC			+5V
21	Output	IRQ	_INT6
22	Input	R/W	_PRWD	_PRW via U15	R_W				CIARW
23	Input	CS	_VMA and A13 via a 74LS32				_EVEN_CIA	_VMA and A13 via a 74LS32	_CIA1
24	Input	FLAG	_INDEX
25	Input	O2	E				E via R109	E	ECLK
26..33	I/O	D7..D0	PD15..PD8		D15..D8				D31..D24
34	Input	RES	_RES		_BRST	_RESET			_IORST
35..38	Input	RS3..RS0	A11..A8						CIADR11..CIADR8
39	I/O	SP	BUSY		PBUSY	BUSY via EMI522		BUSY via RP30, EMI19	PBUSY
40	I/O	CNT	POUT		PPOUT	POUT via EMI523		POUT via RP30, EMI20	PPOUT

PLCC package pinout for Amiga use

Pin	Type	Name	Signal name
			CIA-A			CIA-B
			A600	A1200	A4000	A600	A1200	A4000
1	Power	GND	GND
2	I/O	PA0	unused		OVL	BUSY via E521		PBUSY
3	I/O	PA1	_LED			POUT via E522		PPOUT
4	I/O	PA2	_CHNG			SEL via E523 and RI via Q571, R571, E558		PSEL
5..6	N/C	NC	unused
7	I/O	PA3	_WPROT			DSR via U29, E555		_DSR
8	I/O	PA4	_TRK0			CTS via U29, E554		_CTS
9	I/O	PA5	_RDY			CD via U29, E556		_CD
10	I/O	PA6	_FIRE0		_FIR0	RTS via U28, E553		_RTS
11	I/O	PA7	_FIRE1		_FIR1	DTR via U28, E557		_DTR
12	I/O	PB0	PPD0			_STEP
13	I/O	PB1	PPD1			DIR
14	I/O	PB2	PPD2			_SIDE
15	I/O	PB3	PPD3			_SEL0
16	I/O	PB4	PPD4			_SEL1
17	I/O	PB5	PPD5			_SEL2
18	I/O	PB6	PPD6			_SEL3
19	I/O	PB7	PPD7			_MTR
20	Output	_PC	_STROBE via E511		_PSTROBE	unused
21	Input	TICK	_VSYNC			_HSYNC		_HBS
22	Power	VCC	VCC		+5V	VCC		+5V
23	Output	_INT	_INT2			_INT6
24	Input	_W	R_W		CIARW	R_W		CIARW
25	Input	_CS	_ODD_CIA		_CIA0	_EVEN_CIA		_CIA1
26	Input	_F	_ACK via E520		_PACK	_INDEX
27	Input	E	E		ECLK	E		ECLK
28	N/C	NC	unused
29..36	I/O	D7..D0	D7..D0	D23..D16		D15..D8	D31..D24
37	Input	_RESET	_RST		_IORST	_RST		_IORST
38..39	Input	RS3..RS2	A11..A10		CIADR11..CIADR10	A11..A10		CIADR11..CIADR10
40	N/C	NC	unused
41..42	Input	RS1..RS0	A9..A8		CIADR9..CIADR8	A9..A8		CIADR9..CIADR8
43	I/O	S	_KB_DATA		_KBDAT	BUSY via E521		PBUSY
44	I/O	C	_KB_CLOCK		_KBCLK	POUT via E522		PPOUT

DIP package pinout for 8-bit use

Pin	Type	Name	Signal name
			A2232	1571	1581
1	Power	VSS	GND
2	I/O	PA0	*DCD0	unused	SIDE0
3	I/O	PA1	*DCD1	unused	/RDY
4	I/O	PA2	*DCD2	unused	/MOTOR
5	I/O	PA3	*DCD3	unused	connected to SW1
6	I/O	PA4	*DCD4	unused	connected to SW1
7	I/O	PA5	*DCD5	unused	POWER_LED
8	I/O	PA6	*DCD6	unused	ACT_LED
9	I/O	PA7	unused		/DISK_CHANGE
10	I/O	PB0	*CTS0	unused	DATA_IN
11	I/O	PB1	*CTS1	unused	DATA_OUT
12	I/O	PB2	*CTS2	unused	CLK_IN
13	I/O	PB3	*CTS3	unused	CLK_OUT
14	I/O	PB4	*CTS4	unused	ATN_ACK
15	I/O	PB5	*CTS5	unused	FAST_SER_DIR
16	I/O	PB6	*CTS6	unused	/WPRT
17	I/O	PB7	connected to TOD	unused	ATN_IN
18	Output	PC	unused
19	Input	TOD	connected to PB7	unused	connected to J1
20	Power	VCC	+5		VCC
21	Output	IRQ	*6510_IRQ1	_IRQ
22	Input	R/W	6510_RW	R/_W
23	Input	CS	*ACIA7	connected to U5	/6526SEL
24	Input	FLAG	unused		ATN_IN (via U7)
25	Input	O2	6551_CLK	PHI_2
26..33	I/O	D7..D0	MD7..MD0	D7..D0	DATA7..DATA0
34	Input	RES	*6510_RESET	_RES	_/RESET
35..38	Input	RS3..RS0	MA4..MA1	A3...A0	ADR3..ADR0
39	I/O	SP	RXD0	connected to U19	connected to U13
40	I/O	CNT	*CTS0	connected to U19	connected to U13

Copyright © 2002-2004 Ronald van Dijk - All rights reserved
Last update: 10 January 2004